This article is for MacBook logic board component-level repair professionals,written byIT-Tech Online, the Mac repair specialist in Melbourne, Australia.

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We will discuss the creation of CPU main power rail – PPVCC_S0_CPU. The MacBook Air 13” 2015-2017 logic board schematics 820-00165 will be used as references.

When the SMC (System Management Controller) receives a valid ALL_SYS_PWRGD signal, after 99 milliseconds delayed, SMC will send out SMC_DELAYED_PWRGD. The creation of CPU main power rail PPVCC_S0_CPU will be controlled by the ALL_SYS_PWRGD and SMC_DELAYED_PWRGD signals.

1. The ALL_SYS_PWRGD signal, renamed as PM_PCH_PWROK, is fed to PCH as control signal PCH_PWROK and APWROK.
2. When PCH receive APWROK signal, PCH will read ME codes from the SPIROM U6100. The ME (Intel Management Engine) codes are part of EFI codes stored in the SPIROM chip. The ME codes are coupled with individual PCH. It means if you change a PCH, you must replace the ME codes with a “clean” version and perform the “coupling” again.
3. The ALL_SYS_PWRGD and PM_SLP_S3_L signals will go through the AND-logic gate U1930. U1930 then send out CPU_VCCST_PWRGD signal to PCH and PCH send out CPU_VR_EN signal to enable CPU power management chip U7200.
4. When CPU power management chip U7200 receives CPU_VR_EN signal, U7200 will create the PPVCC_S0_CPU power rail. The voltage of PPVCC_S0_CPU power rail is 1.9V. This is the “base” voltage. When U7200 receive the voltage IDs from the CPU later, this base voltage will be adjusted to around 1.7V. This voltage value can be used to determine whether or not the CPU shoots out the IDs signal.

5. After creating the PPVCC_S0_CPU power rail, U7200 sends out CPU_VR_READY signal to inform PCH that the base PPVCC_S0_CPU voltage has been created.
6. Meanwhile, the SMC_DELAYED_PWRGD signal goes through an AND-logic gate, renamed as PM_PCH_SYS_PWROK and sent to PCH. PCH, in turn, extracts the CPU voltage IDs info from ME codes and send to CPU power management IC U7200.
7. PCH will use ME codes info to set and output system clocks.
8. The CPU/PCH will output platform reset signal PLT_RESET_L, the voltage is 1.05V. The PLT_RESET_L signal is also a very important signal. It marks the end of power rails creation. CPU and operating system (OS) will take control of the whole system.