MacBook logic board power rails and ALL_SYS_PWRGD

Apple logic board S3 power rails creation

1. The U0500 CPU/PCH outputs PM_SLP_S5_L control signal to inform the SMC (System Management Controller) that the MacBook power state transition will begin.
2. TheU0500 CPU/PCH then outputs PM_SLP_S4_L signal to U7501 PMIC to enable PP5V_S3 power rail. PP5V_S3 power rail is the first S3 state power rail and the voltage is 5V.

3. PM_SLP_S4_L signal goes pass resistor R8112, renamed as P3V3S3_EN, to enable power rail PP3V3_S3. The voltage of PP3V3_S3 power rail is 3.3V.
4. PM_SLP_S4_L signal goes pass resistor R8116, renamed as P1V8S3_EN to create power rail PP1V8_S3. The voltage of PP1V8_S3 power rail is 1.8V.
5. PM_SLP_S4_L signal goes pass 20k-ohm resistor R8116, renamed as DDRREG_EN to create PP1V2_S3 power rail. PP1V2_S3 power rail is used for power the DDR3 memory chips, the voltage is 1.2V.
6. PM_SLP_S4_L signal goes pass 100-ohm resistor R8117, renamed as USB_PWR_EN to enable USB port power VBUS. The USB port power rail VBUS voltage is 5V.
7. The PM_SLP_S4_L control signal is also used to enable touchpad and Bluetooth devices.

Note: These S3 power rails are not created at the same time. The RC delay circuits are used to control the delay time, therefore the timing. By changing the values of resistors and capacitors, we can get the delay time as we want.

Apple logic board S0 power rails creation

1. The U0500 CPU/PCH then outputs PM_SLP_S3_L signal to transform the Mac logic board power state from S3 to S0 state (power on).
2. The PM_SLP_S3_L control signal goes pass resistor R8187, renamed as P5VS0_EN, to create PP5V_S0 power rail. The voltage of PP5V_S0 power rail is 5V.
3. The PM_SLP_S3_L control signal goes pass 20k-ohm resistor R8186, renamed as P3V3S0_EN, to create PP3V3_S0 power rail. The voltage of PP3V3_S0 power rail is 3.3V.
4. The PM_SLP_S3_L control signal goes pass resistor R8185, renamed as P1V05S0_EN, to create PP1V05_S0 power rail. The voltage of PP1V05_S0 power rail is 1.05V. This power rail is used by the Intel CPU/PCH and its system buses.
5. The PM_SLP_S3_L control signal goes pass an AND-logic gate U8180, renamed as PM_SLP_S3_BUF_L. The AND_logic gate is used to increase the strength of the PM_SLP_S3_L control signal. The voltage of PM_SLP_S3_BUF_L control signal is 3.3V.

6. The PM_SLP_S3_BUF_L control signal goes to U7870 switch create PP1V5_S0 power rail. The voltage of PP1V5_S0 power rail is 1.5V.
7. The 3.3V PM_SLP_S3_BUF_L control signal is also used as a power rail to poll up ALL_SYS_PWRGD control signal via a 10K-ohm resistor R8167. This is why we need a powerfol version of PM_SLP_S3_BUF_L instead of the weak version of PM_SLP_S3_L.

Note: These S0 power rails are not created at the same time. The timing is determined by the PM_SLP_S3_L control signal and the associated RC delay circuits.

The importance of ALL_SYS_PWRGD signal

Apple has developed a complex validation mechanism to ensure all the power rails being created are stable and good (GD stands for good) for use. If all the power rails are good, then a valid ALL_SYS_PWRGD signal will be produced. ALL_SYS_PWRGD voltage is 3.3V.

A valid ALL_SYS_PWRGD signal checks these power rails: PP1V8_S3, PP5V_S3, PP1V2_S3, PP1V05_S0, PP5V_S0, PP3V3_S0, PP1V5_S0. Any of these S3 or S0 state power rails malfunction will poll down the ALL_SYS_PWRGD signal and terminate the normal power-on process of Apple computers.

The ALL_SYS_PWRGD signal will be reported to SMC. SMC will process this signal and prepare to create the last power rail – CPU/PCH Vcore power rail.